The prior art is replete with network architectures for the interconnection of a plurality of computers, processors, or other computing devices. For example, some satellite radar applications may employ many interconnected integrated circuit (“IC”) processing elements in an electronics enclosure of multiple circuit card assemblies. In addition, current design efforts for future aerospace, satellite, and commercial aircraft applications may contemplate the use of a large number of network-connected IC based processors. For such applications, the network connection topology should strive to minimize size, weight, power consumption, and be appropriate for use in a space flight environment. The topology should be scalable for use with different numbers of IC processing elements, and fault tolerant for long mission life without repair. The physical size of the network architecture should fit well within the practical packaging constraints, such as circuit card size, connector size, number of input/output pins, and electronic cabinet size.
One prior art network architecture for use in a satellite radar application employs a centralized switch network using a number of switches. In such an architecture, a switching element may include individual connections to a number of IC processing elements. In turn, the switching element is connected to a higher level (or centralized) switching element. Input/output connections may also be provided by these switching elements. The hierarchy of switches may be extended to include more than two levels to support a high number of IC processing elements. Unfortunately, the switches in this type of network architecture contain the switching intelligence and consume operating power, which can be problematic in a practical application. In addition, the use of hierarchical switching elements can cause input/output congestion at the higher level switches, resulting in slower performance. Furthermore, although such an architecture can accommodate larger numbers of processing elements via additional levels of switching, the addition of more switches necessarily results in an increase in operating power requirements.
Another prior art network architecture employs a fully connected mesh distributed topology, where each network node is directly connected to every other network node. Such a topology provides an optimized bandwidth across every possible path at the expense of increased operating power and physical size. Such an architecture is impractical because each network node would be required to have an extremely large number of network ports to support the mesh interconnections.
Accordingly, it would be desirable to have a network architecture that addresses connectivity issues in a network having a very large number of network nodes. In addition, it would be desirable to have a network architecture that significantly simplifies the switching, routing, and connectivity of the network, relative to conventional solutions, while providing high fault tolerance, satisfying conservative physical space requirements, satisfying low operating power specifications, and maintaining a low practical deployment cost. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.